1. Field of the Invention
The present invention relates to the field of direct digital frequency synthesis. One possibility for direct digital synthesis DDS of frequencies is represented schematically in FIG. 1 and is described in detail in the text that follows.
2. Discussion of Background Information
It is known in the prior art, from DE 44 42 403 C2 or the corresponding U.S. Pat. No. 5,699,005 A, that when digital clock-controlled signal processing devices are used, interference signals can arise directly or through connected power supply or signal lines over a wide frequency range. The cause of this clock-related interference is current peaks in the clock-controlled device which result from activation of a number of switching stages. The higher the clock frequency is in this context, the larger the current peaks become. This document proposes carrying out modulation of the clock frequency to suppress the interference so that the energy content of the interference signal is not concentrated at one specific spectral line and its harmonics, but instead the energy content is distributed as uniformly as possible over a wider frequency range. To this end, a random delay time is added to the output signal.
U.S. Pat. No. 4,410,954 describes a digital frequency synthesizer for synthesizing a defined frequency wherein a phase increment is fed at a clock rate to a combination of adder and accumulator. The periodic overflow of the accumulator results in the desired frequency. To avoid interference, the phase increments are varied by addition or subtraction of a noise signal either to the input signal or the output signal of the accumulator during at least one clock cycle. By this means, the periodicity of the overflow of the accumulator is randomly varied about its average value. Here, too, the energy content of the interference is distributed from a few discrete frequencies over a larger frequency range, and the intensity of the individual interference lines is thereby reduced.
J. Vankka, “A Direct Digital Synthesizer with a Tunable Error Feedback Structure”, IEEE Transactions on Communications, Vol. 45, No. 4, April 1997, pp. 416-420, describes a direct digital synthesizer (DDS) in which high spectral purity is achieved through a complex chain of frequency dividers, filters, mixers and oscillators. The basic concept here relates to controllable feedback of errors (error feedback).
U.S. Pat. No. 6,219,397 describes a frequency synthesizer with low phase noise that is based on a phase-locked loop (PLL) in which a divider with a fractional rational division ratio is used. The frequency synthesizer here uses a high-order sigma-delta modulator to shape the phase noise (noise shaping) in order to suppress quantization errors (fractional spurs).
P. O'Leary et al., “A Direct-Digital Synthesizer with Improved Spectral Performance”, IEEE Transactions on Communications, Vol. 39, No. 7, July 1991, pp. 1046-1048, describes suppression of interference in a direct digital synthesizer DDS wherein first-order noise shaping is used to reduce interference effects through phase truncation, which is to say through the reduction of phase information to a defined number of bits m as part of digital synthesis. A first-order adder stage is used for the noise shaping here.